1. Field of the Invention
This invention relates to a method and a circuit for applying vectors to a storage device, and more particularly, to those used in a burn-in process of a semiconductor integrated circuit incorporating a large-scaled storage device and a logic circuit.
2. Description of the Prior Art
Conventionally, a burn-in process was conducted for semiconductor integrated circuits to ensure a certain quality by removing defective products. The term "burn-in" pertains to a process of activating semiconductor integrated circuits under a high temperature condition for a predetermined time, e.g. ten hours, in order to apply a stress to the semiconductor integrated circuits and find out any which malfunctions in the initial operation.
FIG. 12 shows a schematic view of a conventional semiconductor integrated circuit, that is, it includes DRAM 2 which is a dynamic memory device. The semiconductor integrated circuit 1 incorporated DRAM 2 and a logic circuit 3. DRAM 2 includes an input circuit 21 at its input end and an output circuit 22 at its output end. The logic circuit 3 includes multiplexers 31 and 32 located upstream of the input of the input circuit. Similarly, the logic circuit 3 includes multiplexers 33 and 34 located downstream of the output circuit 22. These multiplexers 31, 32, 33 and 34 are supplied with a mode selection signal TM from the exterior. The mode selection signal TM is a signal for changing the semiconductor integrated circuit 1 to a DRAM test mode or a normal mode. The multiplexers 31 and 32 are configured to be switched by the mode selection signal TM to selectively output an input from external signals IN1 through INn or an input from the logic circuit to the input circuit 21. Similarly, the multiplexers 33 and 34 are configured to be switched by the mode selection signal TM to selectively output to output terminal OUT1 through OUTn or the logic circuit 3. That is, the multiplexers 31, 32, 33 and 34 enable direct access to DRAM 2 from the exterior when DRAM 2 is tested.
When the mode selection signal TM indicates the DRAM test mode, the external signals IN1 through INn are transferred to the input circuit 21 of DRAM 2, and an output signal from the output circuit 22 of DRAM 2 is released from external terminals OUT1 through OUTn. When the mode selection signal TM indicates the normal mode, a signal from the logic circuit 3 is transferred to the input circuit 21 of DRAM 2, and the output from the output circuit 22 of DRAM 2 is treated in the logic circuit 3.
FIG. 13 is a block diagram showing the interior structure of DRAM 2 referred to above. As shown in FIG. 13, the input circuit 21 is supplied with a load address signal RA0-i, column address signal CA0-k, segment address signal SA0-j, write data signal D0-n, clock signal CLK, read-out signal RD, write signal WT, and refresh signal REF. These signals are details of the external signals IN1 through INn. Output from the output circuit 22 are read-out data signals Q0 through Qn. These signals are details of the output signals OUT1 through OUTn. DRAM 2 has a refresh counter and control circuit 23, segment address decoder 24 and control circuit 25.
DRAM 2 also has a plurality of segments SG1 through SG4 each including a column decoder 26, memory array 27 and a row decoder 28. The column decoder 26 is supplied with a complementary signal which is shaped in waveform from the column address signal CA0-k, and a control signal from the segment address decoder 24. The segment address decoder 24 is supplied with the segment address signal SA0-j. The memory array 27 includes a plurality of memory cells in a matrix alignment. The row decoder 28 is supplied with a signal from the segment address decoder 24 and a complementary signal from the refresh counter and control circuit 23. The complementary signal from the refresh counter and control circuit 23 is the complementary signal of the row address RA0-i input into the refresh counter and control circuit.
A first sense amplifier S/A peculiar to DRAM is contained in the memory array 27. Further provided is a data IN/OUT circuit 29 for executing write and read in these segments SG1 through SG4. The data IN/OUT circuit 29 is supplied with a signal made by waveform-shaping the write data signal D0-n in the input circuit 21, and a control signal from the control circuit 25 which is supplied with the read-out signal RD and the write signal WT.
With reference to FIG. 13, behaviors of the semiconductor integrated circuit are briefly explained.
For writing, the row address signal RA0-i, segment address signal SA0-j and column address signal CA0-k are input to the input circuit 21. These signals determine one of the memory arrays 27. When the read-out signal RD is selected in this status, data is transferred from the memory cell to the data IN/OUT circuit 29. Then, it is transferred to the output circuit 22 and released therefrom as the output signal Q0-n.
In this manner, for write and read operation, a single segment is selected. In contrast, under the condition with the refresh signal REF supplied, the segment address decoder 24 receives the refresh signal REF, and results in all of the segments SG1 through SG4 being selected. Selection of a row address relies on the signal from the refresh counter and control circuit 23.
It will be understood also from FIG. 12 that, in most cases, terminals necessary for the substantial operation of the logic circuit 3 are commonly used as the input terminals IN1 through INn and output terminals OUT1 through OUTn, in order to diminish the number of pins in the entirety of a single semiconductor integrated circuit and to permit direct access to DRAM 2 even after assembly. Therefore, for access to DRAM 2, one of normal operation or test operation must be selected. That is, for read and write operation of DRAM 2, it must be selected through the logic circuit 3 whether DRAM 2 should be operated normally or for a test.
For a burn-in process of the semiconductor integrated circuit 1 of this type, different vectors are supplied to DRAM 2 and the logic circuit 3, independently, or a vector for the logic circuit 3 is used for read and write of all memory cells. However, the former process of applying different vectors are applied independently to DRAM 2 and the logic circuit 3 requires a longer burn-in time to conduct it independently for DRAM 2 and the logic circuit 3. The latter process of accessing to all memory cells by using a vector for the logic circuit 3 is actually impossible because of problems in vector length of a burn-in device. The term "vector" herein means signals such as address, data and instruction which are necessary for activating DRAM 2 and the logic circuit 3.